1. Technical Field
The present application relates to interface devices, and more specifically, to a flexible and programmable flash memory interface device capable of interfacing with various kinds of flash memory devices with varying protocols.
2. Description of Related Art
Flash memory is a form of EEPROM (Electrically-Erasable Programmable Read-Only Memory) that allows multiple memory locations to be erased or written in one programming operation. It is a Non-Volatile Read Write Memory (NVRWM) commonly used in memory cards, USB flash drives, MP3 players, digital cameras, mobile phones, etc. There are different kinds of flash memory devices available in the market today. The flash memory stores a correctable control program, which is used instead of an auxiliary memory.
NOR-based flash has long erase and write times, but has a full address/data (memory) interface that allows random access to any location, which makes it suitable for storage of program code that needs to be infrequently updated, such as a computer's BIOS or the firmware of a set-top box. The endurance of NOR-based flash is 10,000 to 1,000,000 erase cycles. NOR-based flash was the basis of early flash-based removable media; Compact Flash was originally based on this technology, although later cards moved to the cheaper NAND flash.
NAND flash has faster erase and write times, higher density, and lower cost per bit than NOR flash, and ten times the endurance. However its I/O interface allows only sequential access to data. This makes it suitable for mass-storage devices such as PC cards and various memory cards, and it is somewhat less useful for computer memory.
Serial Flash is a small, low-power flash memory that uses a serial interface for sequential data access. Serial flash uses fewer wires than parallel flash memories to transfer data to and from a system. A reduction in board space, power consumption and system cost are some of the benefits of the lower pin count interface for serial flash memories.
The flash memory is divided into a NAND flash memory and a NOR type flash memory. The NOR type flash memory uses an interface method as an SRAM or as a ROM to easily construct a circuit with a processor. Further, the NAND flash memory is more sophisticated using the interface method than the NOR type flash memory and has an advantage of lower economic costs. However, the NAND flash memory has a higher degree of integration than the NOR flash memory.
These days, a number of vendors are providing NOR, NAND and SERIAL flashes having varying protocols and interfacing programs, and hence no common protocol is being followed by these vendors. The result of these flashes is that every new flash that is brought out in the market has its own set of commands, modes and operations that can be performed on them. This becomes a problem when the memory interface modules interacting with these devices have to be modified for every different device. The IPs (Intellectual Property) in the subsystem is not configurable, thus requiring manual changes depending upon nuances of different chips. Many SOCs (System on Chip) have more than one type of flash memory devices in the subsystem. This entails having more than one memory interface module to interact with them. In order to reduce the pin count of the SOC, the output pins of these multiple modules have to be multiplexed leading to an increase in glue logic, and thus area.
FIG. 1 represents a conventional structure for a flash memory interface system interacting with NAND, NOR and SERIAL flash memories. The interface has three different modules, one for each type of flash memory device. The output pins of these modules are multiplexed at the output of the subsystem, which drives a shared bus. The shared bus in turn drives the pins of the memory blocks. These modules interact with the external world through a decoder or a router that decodes the incoming address bits and routes it to the required module.
The modules offer little or no flexibility to accommodate new protocols, or even new modes. Multiplexing the pins of these three modules adds to the glue logic, and therefore increases a usage area and a delay. Even when the memory devices come up with optimizations in the protocol which offer more efficient access times (for example, removing dummy cycles), incorporating them in the interface subsystem means changing the RTL and going through the entire design cycle which is both time and money consuming.
There is a need of a versatile/flexible solution through a proposed flexible and programmable flash memory interface device, which can overcome the above mentioned problems. Moreover, the proposed memory interface device allows support for maximum features of different memories available in the market for easy integration.